A. Technical Field
The present invention relates generally to secure microcontroller systems and/or modules, and more particularly to systems and methods related to the protection of embedded memories and the enablement of self-securing memory elements within a memory system architecture.
B. Background of the Invention
The importance of data security within today's computing systems is well understood by one of skill in the art. Significant research and development has occurred across numerous markets in an attempt to establish security protocols and architectures that maintain the integrity of data stored within memory systems. Although these efforts have resulted in major improvements to secure systems, there still remains meaningful risk that data stored within a secure system can become compromised.
The difficulty in designing and maintaining a secure computing system is related to the daunting task of addressing all of the potential vulnerabilities of the system that may compromise data security. One such vulnerability is the manner in which encryption keys are generated and maintained within the secure system as well as how these keys are implemented in storage operations. If encryption keys are not derived from a sufficiently random and/or unique source, then the keys could potentially be replicated by an attacker and used to obtain information from the system. For example, if an individual is able to predict a pseudo-random number used to seed encryption keys within the system (e.g., understand the algorithm used to generate the number), then that individual could derive encryption keys to decrypt data stored in the system. As a result, security engineers are constantly looking for ways in which the randomness of keys may be increased.
A second vulnerability relates to the address mapping of a memory that defines the process in which data is stored across a plurality of memory cells. In some memory systems, address decoders effectively scramble the storage sequence of data across memory cells in accordance to a pre-defined memory mapping. This mapping is not unique to a specific memory module but shared across compatible memories that may be found in many devices. As a result, once a memory mapping is compromised within one device, that memory map can be applied to other compatible memories to attack stored data in other devices.
FIG. 1 illustrates a standard memory architecture used within various computing systems. In certain memory systems, the design has a physical arrangement with a dense memory cell array and a less compact peripheral area that includes address decoder, multiplex, and sense circuits as well as inputs and outputs. For some nonvolatile memories, the peripheral area also contains sequencer circuitry that supports erase and programming operations. One skilled in the art will recognize that the general concept of data security, and corresponding systems and methods, are relevant in a vastly diverse set of computing systems, all of which are relevant to the present invention.
The exemplary memory system 100 includes a plurality of memory cells that are addressed via bit-lines and word-lines. The system 100 also includes an address decoder 110 which is coupled to an address bus and identifies a location/address within the cell array based on an input from the address bus. The system 100 includes read/write circuitry 120 that is coupled to a data bus. The read/write circuitry 120 writes data into one or more cells or reads data from one or more cells based on storage instructions and corresponding memory address(es). A charge pump controller 130 may also be present in the memory system 100.
In certain memory systems, both bit and word lines are well-ordered and mapped according to a well-known architecture. For example, as shown in FIG. 2, bit-lines and word-lines are ordered and mapped sequentially from 0 to n−1, and 0 to m−1, respectively. Referring to FIG. 2, lines 210-213 within the read/write circuitry are structured in such a manner that allows data to be read and written in a pre-defined and known algorithm across the memory cells. Lines 220-223 within the address decoder are structured in a corresponding order/map to the structure within the read/write circuitry. As such, operation within the memory may not necessarily function in a purely sequential manner but nevertheless operates in a consistently repeatable pattern across multiple memory systems. Accordingly, the security of the memory may be compromised once this repeatable pattern is identified and be used to attack other devices using the same map.
Data remanence further complicates security within a memory system. It is well known that both volatile and non-volatile memory cells can exhibit data remanence. After erase or overwrite operations, the erased or overwritten data can be reconstructed using well-structured data patterns, exploiting the residual physical data representation. Similarly, data in volatile memories may persist after removal of system power; this is especially pronounced in low-temperature environments. This data remanence behavior further increases the importance of security processes employed in storing data within memory.
What is needed are systems, devices and methods that address the above-described concerns.